This invention relates to integrated circuit (IC) structures and processes that include a strained silicon or silicon germanium (Si/SiGe) layer. More particularly, this invention relates to formation of a structure having a strained Si/SiGe layer on an insulator layer which is useful for fabricating high speed devices such as complementary metal-oxide-semiconductor (CMOS) transistors and other metal-oxide-semiconductor field effect transistor (MOSFET) applications.
Electron and hole mobility in strained silicon or silicon germanium layers has been shown to be significantly higher than that in bulk silicon. For example, measured values of electron mobility in strained Si at room temperature are about 3000 cm2/Vs as opposed to 400 cm2/Vs in bulk silicon. Similarly, hole mobility in strained SiGe with high Ge concentration (60%˜80%) reaches up to 800 cm2/Vs, which is about 5 times the hole mobility in bulk silicon of 150 cm2/Vs. MOSFETs with strained-Si channels have been experimentally demonstrated to have enhanced device performance compared to devices fabricated in conventional (unstrained) silicon substrates. Potential performance improvements include increased device drive current and transconductance, as well as the added ability to scale the operation voltage without sacrificing circuit speed in order to reduce the power consumption.
Strained-Si layers are the result of biaxial tensile stress induced in silicon grown on a substrate formed of a material whose lattice constant is greater than that of silicon. The lattice constant of germanium is about 4.2 percent greater than that of silicon, and the lattice constant of a silicon-germanium alloy is nearly linear with respect to its germanium concentration. As a result, the lattice constant of a SiGe alloy containing fifty atomic percent germanium is about 1.02 times greater than the lattice constant of silicon. Epitaxial growth of silicon on such a SiGe substrate will yield a silicon layer under tensile strain, with the underlying SiGe substrate being essentially unstrained, or “relaxed.” A structure and process that realize the advantages of a strained-Si channel structure for MOSFET applications are taught in commonly-assigned U.S. Pat. No. 6,059,895, which discloses a technique for forming a CMOS device having a strained-Si channel on a SiGe layer, all on an insulating substrate.
The underlying conducting substrate for MOSFETs and bipolar transistors or the interaction of the underlying substrate with the active device regions in CMOS are undesirable features which limit the full performance of high speed devices. To resolve the problem, in Si technology, an insulating layer is usually used to isolate the active device region from the substrate, by creating Silicon-On-insulator (SOI) wafers to replace bulk Si material for device fabrication. Available technology to achieve SOI wafers includes Separation by Implanted Oxygen (SIMOX), bonding and etchback Silicon-On-Insulator (BESOI), separation by implanted hydrogen also known as the Smart-Cut® process which is described in U.S. Pat. No. 5,374,564, or the combination of the last two processes for making ultra-thin SOI, described in U.S. Pat. No. 5,882,987.
When Si in an SOI wafer is substituted by strained Si or SiGe (Si/SiGe) layers for high speed applications, two methods are generally used to produce strained Si/SiGe-on-insulator structures. In one method, thermal mixing is used to produce a relaxed SiGe-on-insulator structure (SGOI), followed by epitaxial growth of strained Si on SGOI. This thermal mixing method is illustrated in FIGS. 1(a)-(c). A SiGe layer 13 is deposited on an SOI substrate comprising silicon substrate 10, insulator or oxide layer 11 and silicon layer 12, as shown in FIG. 1(a). Thermal mixing is then performed, to produce the structure shown in FIG. 1(b) which comprises substrate 10, insulator layer 11, and SiGe layer 14. During thermal mixing, germanium is rejected from the oxide during high temperature oxidation, and the final SiGe concentration and relaxation in layer 14 is a function of the initial SiGe concentration in layer 13, its thickness, and the final thickness of SiGe layer 14. Following thermal mixing, oxide is stripped from the top surface of the structure. Finally, strained Si layer 15 is grown on SiGe layer 14, as shown in FIG. 1(c).
While thermal mixing is a promising method to make strained Si/SiGe-on-insulator, it has draw backs. In the thermal mixing method, a SiGe-on-insulator structure is first formed, then strained Si is grown on the SiGe. Strained Si deposition on SiGe may leave a non-ideal interface with O and C residue, which may affect device performance or yield. In addition, SiGe after thermal mixing is usually not fully relaxed. In order to achieve high strain in the strained Si, high concentration SiGe is needed as the template for strained Si growth. The high concentration SiGe will lead to integration complexity and potentially yield degradation.
The other method generally used to produce strained Si/SiGe on insulator structures involves wafer bonding. Specifically, a first wafer bonding method involves bonding relaxed SiGe onto an insulator followed by strained Si/SiGe growth. This first wafer bonding method is described in U.S. Pat. No. 6,524,935, and is illustrated in FIGS. 2(a)-2(d). The method begins with growing an epitaxial relaxed SiGe layer 21 on a first silicon substrate 20, as shown in FIG. 2(a). Next, hydrogen is implanted into the SiGe layer 21 to form a hydrogen-rich defective layer (not shown). The surface of the SiGe layer 21 is smoothed by chemical-mechanical polishing (CMP). Then, the surface of the first substrate is bonded to the surface of a second substrate comprising bulk silicon 22 and an insulator layer 23, as shown in FIG. 2(b). Specifically, the smoothed surface of the SiGe layer 21 is bonded to the insulator layer 23, which is typically SiO2. Bonding the two substrates together is accomplished by placing the surface of the first substrate against the surface of the second substrate resulting in a weak chemical bond which holds the two substrates together. A thermal treatment is usually performed to the bonded wafer pair to strengthen the chemical bonds at the joined interface. Following bonding, the two substrates are separated at the hydrogen-rich defective layer, resulting in the structure shown in FIG. 2(c) which comprises second substrate 22, insulator layer 23 and a portion of SiGe layer 21. The top surface of SiGe layer 21 in this separated structure may be smoothed by CMP. Finally, in FIG. 2(d), strained Si layer 24 is epitaxially grown on SiGe layer 21.
This wafer bonding method suffers from process complications. The as-bonded SiGe on insulator is usually too thick, and therefore thinning of SiGe is required before strained Si deposition, which is a non-trivial process. In addition, strained Si deposition on SiGe may leave a non-ideal interface with O and C residue, which may affect device performance or yield.
A second wafer bonding method involves directly bonding strained Si/SiGe onto an insulator. This second wafer bonding method is described in U.S. Pat. No. 6,603,156, and is illustrated in FIGS. 3(a)-3(e). The method begins with growing a relaxed SiGe layer 31 on a first silicon substrate 30, as shown in FIG. 3(a). A strained-Si layer 32 is next formed on strain-inducing SiGe layer 31, as shown in FIG. 3(b). Then, the first substrate is bonded to a second substrate comprising bulk silicon 33 and an insulator layer 34, as shown in FIG. 3(c). Specifically, the two structures are bonded such that the insulating layer 34 is between strained-Si layer 32 and second substrate 33, and the strained-Si layer 32 directly contacts the insulating layer 34, as shown in FIG. 3(d). The initial strain-inducing layer 31 is then removed to expose the surface of the strained-Si layer 32 and yield a strained-Si-on-insulator (SSOI) structure. Strain-inducing layer 31 may be removed by CMP, wafer cleaving (smart cut), or chemical etching. A chemical etching process such as HHA (hydrogen peroxide, hydrofluoric acid, and acetic acid) selective to Si is preferred so that the SiGe layer 31 is fully removed stopping on the strained-Si layer 32.
This second wafer bonding method eliminates the steps of thinning of SiGe and the interface left by strained-Si growth on SiGe, as needed by the first wafer bonding method. U.S. Pat. No. 6,603,156 also teaches that a structure without SiGe between the strained-Si and the insulator is advantageous, as SiGe usually complicates CMOS processes. However, with strained-Si directly on insulator, the thickness of Si is limited due to the critical thickness of the strained layer. For example, strained-Si with 1% of strain is limited to a thickness of about 100 Å, beyond which defects may form in the strained-Si during high temperature process steps. The critical thickness of Si with higher strain is even less. Given that current CMOS technologies require various Si thicknesses for SOI structures, there is a need in the art for a method of forming strained SOI or SGOI structures having the required total Si/SiGe thickness without exceeding the critical thickness of the strained layer.